This invention relates to a semiconductor device and also to a manufacturing technique thereof. More particularly, the invention relates to a semiconductor device having bump electrodes and also to a technique effective for application to the manufacturing technique thereof.
With multi-pin semiconductor devices such, for example, as LCD (liquid crystal display) drivers, a problem is involved in that the chip size increases with an increasing number of electrode pads. This is for the reason that the electrode pad for leading out an electrode of an integrated circuit within a semiconductor chip cannot be made small in size in comparison with the size reduction of element and wiring in view of the securing practice for bonding strength, bonding accuracy and standards on the part of packaging semiconductor chips, so that the chip size is determined depending on the number and size of electrode pads. To avoid this, with the case of multi-pin semiconductor devices, a technique or system is now being adopted wherein electrode pads are arranged in a more inner region of a semiconductor chip where elements and wirings are arranged (i.e. an active region).
It will be noted that semiconductor devices having bump electrodes are disclosed, for example, in Japanese Patent No. 3022565. In this patent, a technique is disclosed wherein a dummy pattern is arranged below electrode pads.